module FreqInterface(
input clk,
input rst_n,
input CS,
input rd_n,
input [7:0] addr,
output reg [31:0] data_rd,
input sig_in
);

always @(posedge clk,negedge rst_n) begin 
	if(!rst_n) begin 
	data_rd<=0;
	end 
	else if((!rd_n)&&(CS)) begin
		case (addr)
		8'd0: data_rd<=FREQ_0;
		8'd1: data_rd<=FREQ_1;
		default :data_rd<=data_rd;
		endcase 
	end 
	else 
		data_rd<=data_rd;
end 
wire [31:0] FREQ_0;
wire  [31:0] FREQ_1;

FreqTest FreqTest_inst
(
	.clk(clk) ,	// input  clk_sig
	.rst_n(rst_n) ,	// input  rst_n_sig
	.test_sig(sig_in) ,	// input  test_sig_sig
	.testnum(FREQ_0) ,	// output [31:0] testnum_sig
	.clknum(FREQ_1) 	// output [31:0] clknum_sig
);


endmodule 